1. Technical Field
The present invention generally relates to a semiconductor apparatus, and more particularly, to a semiconductor memory apparatus, a block decoder therefor, and a decoding method thereof.
2. Related Art
According to the recent trend, a voltage level supplied from outside the semiconductor apparatus has gradually decreased to lower power consumption of a semiconductor apparatus. In some cases, however, the semiconductor apparatus may internally require a voltage having a higher level than the external voltage. Thus, at this time, the semiconductor apparatus uses a voltage pumping circuit.
In particular, a flash memory apparatus requires a voltage of 20V or more, depending on the operation mode thereof. That is, during a program, read, or erase operation of the flash memory apparatus, a high voltage must be supplied to a word line of a memory cell. This operation is performed by a block decoder.
For example, FIG. 1 is a configuration diagram of a conventional semiconductor memory apparatus, illustrating a flash memory apparatus.
Referring to FIG. 1, the semiconductor memory apparatus 100 includes a memory area 101 (including a common source line CSL), a page buffer circuit 103, a block switch 105, a word line decoder 107, and a plurality of block decoders 109-0 to 109-K.
The memory area 101 may be divided into a plurality of blocks 101-0 to 101-K, and each of the blocks has a string structure in which a plurality of memory cells are connected between word lines WL (i.e., WLn, WLn−1, WL0) and bit lines BL (i.e., BLe and BLo). That is, a plurality of memory cells are connected in series to a drain select switch driven by a voltage applied to a drain select line DSL, thereby forming one string, and the final cell of the string is connected to a source select switch driven by a voltage applied to a source select line SSL. Furthermore, a plurality of memory cells connected to one word line WL form one page.
The page buffer circuit 103 is connected to the bit lines extended from the memory area 101, and are configured to transmit and receive data to an input/output control logic (not illustrated). The word line decoder 107 is configured to decode a row address for accessing the memory area 101.
The block decoders 109-0 to 109-K are provided for the respective blocks 109-0 to 109-K, and are configured to apply block select signals to word lines BLKWL0 to BLKWLK, respectively, to control the block switches 105-0 to 105-K.
The block switches 105-0 to 105-K are configured to apply a voltage signal generated by a high voltage generator (not illustrated) to the memory cell blocks 101-0 to 101-K according to the output levels of the block decoders 109-0 to 109-K. For this operation, the block switches 105-0 to 105-K include switches for connecting global word lines GWL (i.e., GWLn, GWLn−1, GWL0) to the memory cell blocks 101-0 to 101-K and include switches for connecting a global drain select line GDSL and a global source select line GSSL to the memory cell blocks 101-0 to 101-K.
The high voltage generator (not illustrated) includes one or more pumps to provide a high voltage according to each operation mode of the semiconductor memory apparatus. Furthermore, the high voltage generated by the high voltage generator is provided to the block switches 105-0 to 105-K through the word line decoder 107. As the block switches 105-0 to 105-K are turned on by the block decoders 109-0 to 109-K, the high voltage is applied to a selected block of the memory area 101.
FIG. 2 is a configuration diagram of the conventional block decoder.
The block decoder 109 illustrated in FIG. 2 includes a block address decoding unit P1 and N1 to N5 configured to output a control signal to a node A in response to an enable signal EN and block address signals XA, XB, XC, and XD.
Furthermore, the block decoder 109 includes a high voltage transmission unit having first and second high voltage switches DHVN and HVP, respectively, connected in series between a high voltage supply terminal VBLC and block word line connection nodes B, respectively, and the second high voltage switch HVP is driven according to a voltage level applied to the node A.
In addition, the block decoder 109 includes select line control circuits P2, N6, and N7 configured to control the voltages of the drain select line DSL and the source select line SSL according to the voltage level of the node A.
The block decoder 109 illustrated in FIG. 2 is provided for each of the blocks 101-0 to 101-K forming the memory area 101 as illustrated in FIG. 1. Accordingly, since the block decoder 109 occupies a large area, the size of the block decoder 109 must be reduced if a high integration of a semiconductor memory apparatus is desired.
Furthermore, the block decoder 109 may include the first and second high voltage switches DHVN and HVP, respectively, to supply the high voltage VBLC to the block word line BLKWL. The high voltage switches DHVN and HVP are designed with a large size for switching high voltages. Therefore, due to the size of the high voltage switches DHVN and HVP, the size of the block decoder 109 may increase.
In particular, the high voltage switch DHVN is designed as a depletion type such that a threshold voltage has a negative (−) value at all times. Accordingly, compared to a general NMOS transistor or high-voltage NMOS transistor HVN, the high voltage switch DHVN is fabricated to have a relatively larger size.
As the high voltage switches, having a large size, are employed and having the block decoder provide for each of the memory blocks, the block decoder 109 may then serve as an obstacle to reducing the size of the semiconductor memory apparatus.
Furthermore, the body of the high voltage switch HVP is connected to a source terminal configured to receive the high voltage VBLC. Therefore, when the high voltage VBLC (for example, 28˜31V) is applied to the source terminal and the body is in a state in which a gate terminal of the high voltage switch HVP is set to 0V, a failure may occur in a gate oxide layer of the high voltage switch HVP. When the high voltage switch HVP is not turned on due to the failure of the gate oxide layer, a high voltage cannot be supplied to the block word line BLKWL, and thus, the circuit may malfunction.